PIC12F683 In Production The Low Pin-count (8) PIC® Flash microcontroller products offer all of the advantages of the well recognized mid-range x14 architecture with standardized features including a wide operating voltage of 2.0-5.5 volts, on-board EEPROM Data Memory, and nanoWatt Technology. Standard analog peripherals include up to 4 channels of 10-bit A/D, an analog comparator module with a single comparator, programmable on-chip voltage reference and a Standard Capture/Compare/PWM (CCP) module.
12f683 datasheet pdf Information:Accurate and, Samsung monochrome laser mfp scx-4521f driver, Unmagal vanda song.
Devices Protected by Microchips Low Pin Count Patent: U.S. Additional U.S. And foreign patents and applications may be issued or pending.
2004 Microchip Technology Inc. PIC12F683 Data Sheet 8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology Preliminary DS41211B. ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, Select Mode, SmartSensor, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. And other countries. Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. Flash/Data EEPROM Retention: 40 years Program Memory Device Flash (words) SRAM (bytes) PIC12F683 2048 2004 Microchip Technology Inc.
PIC12F683 nanoWatt Technology Low-Power Features Standby Current 2.0V, typical Operating Current kHz, 2.0V, typical - 100 MHz, 2.0V, typical Watchdog Timer Current. PIC12F683 Pin Diagram 8-pin PDIP, SOIC, DFN-S GP5/T1CKI/OSC1/CLKIN GP4/AN3/T1G/OSC2/CLKOUT GP3/MCLR/V DS41211B-page GP0/AN0/CIN/ICSPDAT/ULPWU 3 6 GP1/AN1/CIN-/ GP2/AN2/T0CKI/INT/COUT/CCP1 PP Preliminary /ICSPCLK REF 2004 Microchip Technology Inc. When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2004 Microchip Technology Inc.
Preliminary PIC12F683 DS41211B-page 3. PIC12F683 NOTES: DS41211B-page 4 Preliminary 2004 Microchip Technology Inc. The PIC12F683 is covered by this data sheet available in 8-pin PDIP, SOIC and DFN-S packages. Figure 1-1 shows a block diagram of the PIC12F683 device. Table 1-1 shows the pinout description.
PIC12F683 TABLE 1-1: PIC12F683 PINOUT DESCRIPTION Name Function GP5/T1CKI/OSC1/CLKIN GP5 T1CKI OSC1 CLKIN GP4/AN3/T1G/OSC2/CLKOUT GP4 AN3 T1G OSC2 CLKOUT GP3/MCLR/V GP3 PP MCLR V PP GP2/AN2/T0CKI/INT/COUT/CCP1 GP2 AN2 T0CKI INT COUT CCP1 GP1/AN1/CIN-/V /ICSPCLK GP1 REF AN1 CIN- V REF ICSPCLK GP0/AN0/CIN/ICSPDAT/ULPWU. Program Memory Organization The PIC12F683 has a 13-bit program counter capable of addressing program memory space. Only the first (0000h-07FFh) for the PIC12F683 is physically implemented. Accessing a location above these boundaries will cause a wrap around within the first space.
The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1). The Special Function Registers associated with the core are described in this section. Those related to the operation of the peripheral features are described in the section of that peripheral feature. DS41211B-page 8 FIGURE 2-2: DATA MEMORY MAP OF THE PIC12F683 File Address (1) Indirect addr. 00h TMR0 01h. TABLE 2-1: PIC12F683 SPECIAL REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 83 01h TMR0 Timer0 Modules Register 02h PCL Program Counters (PC) Least Significant Byte. PIC12F683 TABLE 2-2: PIC12F683 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 83 81h OPTIONREG GPPU INTEDG 82h PCL Program Counters (PC) Least Significant Byte.
For other instructions not affecting any Status bits, see the Instruction Set Summary. Note 1: Bits IRP and RP1 (Status) are not used by the PIC12F683 and should be maintained as clear. Use of these bits is not recommended, since this may affect upward compatibility with future products. Note 1: A dedicated 16-bit WDT postscaler is available for the PIC12F683. See Section 12.6 Watchdog Timer (WDT) for more information.
Legend Readable bit - n Value at POR DS41211B-page 12 Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT by setting PSA bit to ‘. R/W-0 R/W-0 R/W-0 R/W-0 T0IE INTE GPIE T0IF (1) ( Writable bit U Unimplemented bit, read as 0 1 Bit is set 0 Bit is cleared Preliminary PIC12F683 R/W-0 R/W-0 INTF GPIF bit Bit is unknown DS41211B-page 13. PIC12F683 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: PIE1 PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch) R/W-0 R/W-0 EEIE ADIE bit 7 bit 7 EEIE: EE Write Complete Interrupt Enable bit 1 Enables the EE write complete interrupt 0 Disables the EE write complete interrupt.
R/W-0 U-0 R/W-0 R/W-0 CCP1IF CMIF OSFIF W Writable bit U Unimplemented bit, read as 0 1 Bit is set 0 Bit is cleared Preliminary PIC12F683 R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown DS41211B-page 15. PIC12F683 2.2.2.6 PCON Register The Power Control (PCON) register contains flag bits (see Table 12-2) to differentiate between a: Power-on Reset (POR) Brown-out Detect (BOD) Watchdog Timer Reset (WDT) External MCLR Reset The PCON register also controls the Ultra Low-Power Wake-up and software enable of the BOD. Application Note AN556, Implementing a Table Read (DS00556). 2.3.2 STACK The PIC12F683 family has an 8-level x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. PIC12F683 FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC12F683 Direct Addressing (1) From Opcode RP1 RP0 6 Bank Select Location Select 00h Data Memory 7Fh Bank 0 For memory map detail, see Figure 2-2.
Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear. DS41211B-page 18 0 IRP. Sleep OSC1 Internal Oscillator HFINTOSC 8 MHz LFINTOSC 31 kHz 2004 Microchip Technology Inc. The PIC12F683 can be configured in one of eight clock modes External clock with I/O on GP4 Low gain crystal or Ceramic Resonator Oscillator mode Medium gain crystal or Ceramic Resonator Oscillator mode. External Clock Modes 3.3.1 OSCILLATOR START-UP TIMER (OST) If the PIC12F683 is configured for LP modes, the Oscillator Start-up Timer (OST) counts 1024 oscil- lations from the OSC1 pin, following a Power-on Reset (POR) and the Power-up Timer (PWRT) has expired (if configured wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended.
Figure 3-6 shows the RCIO mode connections. Preliminary PIC12F683 CERAMIC RESONATOR OPERATION ( MODE) PIC12F683 OSC1 To Internal Logic (3) Sleep F ( OSC2 ( may be required for S varies with the oscillator MODE Internal OSC1 Clock PIC12F683 OSC2/CLKOUT / 100 k EXT C EXT DS41211B-page 21. Internal Clock Modes The PIC12F683 has two independent, internal oscilla- tors that can be configured or selected as the system clock source. The HFINTOSC (High-Frequency Internal Oscil- lator) is factory calibrated and operates at 8 MHz. Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency.
U-0 U-0 R/W-0 R/W-0 TUN4 TUN3 W Writable bit U Unimplemented bit, read as 0 1 Bit is set 0 Bit is cleared Preliminary PIC12F683 R/W-0 R/W-0 R/W-0 TUN2 TUN1 TUN0 bit Bit is unknown DS41211B-page 23. PIC12F683 3.4.3 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC uncalibrated (approximate) 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 3-1). 31 kHz can be selected via software using the IRCF bits (see Section 3.4.4 Frequency Select Bits (IRCF)).
Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit (OSCCON) to remain clear. When the PIC12F683 is configured for LP modes, the Oscillator Start-up Timer (OST) is enabled (see Section 3.3.1 Oscillator Start-up (OST)”. PIC12F683 3.6.3 CHECKING EXTERNAL/INTERNAL CLOCK STATUS Checking the state of the OSTS bit (OSCCON) will confirm if the PIC12F683 is running from the external clock source as defined by the FOSC bits in the Configuration Word register (CONFIG) or the internal oscillator. FIGURE 3-7: TWO-SPEED START- INTOSC T T OST. The Fail-Safe condition is cleared after a Reset, the execution of a SLEEP instruction modification of the SCS bit.
While in Fail-Safe condition, the PIC12F683 uses the internal oscillator as the system clock source. The IRCF bits (OSCCON) can be modified to adjust the internal oscillator frequency without exiting the Fail-Safe condition. PIC12F683 3.7.2 RESET OR WAKE-UP FROM SLEEP The FSCM is designed to detect oscillator failure at any point after the device has exited a Reset or Sleep con- dition and the Oscillator Start-up Timer (OST) has expired.
If the external clock mode, monitoring will begin immediately following these events. TMR2IE TMR1IE 000- 0000 0000 0000 (2) IRCF1 IRCF0 OSTS HTS LTS TUN4 TUN3 TUN2 TUN1 MCLRE PWRTE WDTE FOSC2 FOSC1 Preliminary PIC12F683 Bit 0 Value on: Value on POR, BOD all other Resets SCS -110 x000 -110 x000 TUN0 -0 0000 -u uuuu FOSC0 DS41211B-page 29. PIC12F683 NOTES: DS41211B-page 30 Preliminary 2004 Microchip Technology Inc.
MOVLW 0Ch MOVWF TRISIO BCF STATUS,RP0 4.2 Additional Pin Functions Every GPIO pin on the PIC12F683 has an interrupt-on- change option and a weak pull-up option. GP0 has an Ultra Low-Power Wake-up option. The next three sections describe these functions. 4.2.1 WEAK PULL-UPS Each of the GPIO pins, except GP3, has an individually configurable weak internal pull-up. PIC12F683 REGISTER 4-2: TRISIO GPIO TRI-STATE REGISTER (ADDRESS: 85h) U-0 bit 7 bit 7-6: Unimplemented: Read as 0 bit 5-0: TRISIO: GPIO Tri-State Control bit 1 GPIO pin configured as an input (tri-stated GPIO pin configured as an output Note 1: TRISIO always reads 1. 2: TRISIO reads 1 in XT, LP and HS modes.
The Ultra Low-Power Wake-up peripheral can also be configured as a simple Programmable Low-Voltage Detect or temperature sensor. Note: For more information, refer to the Applica- tion Note AN879, Using the Microchip Ultra (DS00879). Preliminary PIC12F683 R/W-0 R/W-0 R/W-0 IOC2 IOC1 IOC0 bit Bit is unknown Low-Power Wake-up Module”. PIC12F683 EXAMPLE 4-2: ULTRA LOW-POWER WAKE-UP INITIALIZATION BCF STATUS,RP0;Bank 0 BSF GPIO,0;Set GP0 data latch MOVLW H7;Turn off MOVWF CMCON0; comparator BSF STATUS,RP0;Bank 1 BCF ANSEL,0;GP0 to digital I/O BCF TRISIO,0;Output high to CALL CapDelay; charge capacitor BSF PCON,ULPWUE;Enable ULP Wake-up. TRISIO RD TRISIO RD GPIO IOC RD IOC Interrupt-on- change To TMR0 To INT To A/D Converter Note 1: Comparator mode and ANSEL determines Analog Input mode. Preliminary PIC12F683 BLOCK DIAGRAM OF GP2 Analog Input Mode Weak GPPU Analog COUT Input Enable Mode COUT 1. PIC12F683 4.2.4.4 GP3/MCLR/V PP Figure 4-4 shows the diagram for this pin.
The GP3 pin is configurable to function as one of the following: a general purpose input as Master Clear Reset with weak pull-up FIGURE 4-4: BLOCK DIAGRAM OF GP3 MCLRE Data Bus MCLRE Reset TRISIO MCLRE RD GPIO. GPIO IOC EN RD IOC Q EN Interrupt-on- change RD GPIO To TMR1 or CLKGEN Note 1: Timer1 LP oscillator enabled.
2: When using Timer1 with LP oscillator, the Schmitt Trigger is bypassed. 2004 Microchip Technology Inc.
( Weak V DD I/O pin Preliminary PIC12F683 DS41211B-page 37. PIC12F683 TABLE 4-1: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO Addr Name Bit 7 Bit 6 05h GPIO 0Bh/8Bh INTCON GIE PEIE 19h CMCON0 COUT 81h OPTIONREG GPPU INTEDG 85h TRISIO 95h WPU 96h IOC 9Fh ANSEL —. Interrupt Service Routine before re-enabling this interrupt.
The Timer0 interrupt cannot wake the processor from Sleep since the timer is shut off during Sleep. 8-bit Prescaler PSA 8 PS 16-bit 16 PSA WDTPS Preliminary PIC12F683 edge (T0SE) control ® Mid-Range MCU Family Data Bus 8 1 SYNC 2 TMR0 Cycles. PIC12F683 5.3 Using Timer0 with an External Clock When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. TIMER1 MODULE WITH GATE CONTROL The PIC12F683 has a 16-bit timer.
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Figure 6-1 shows the basic block diagram of the Timer1 module. Timer1 has the following features: 16-bit timer/counter (TMR1H:TMR1L) Readable and writable Internal or external clock selection Synchronous or asynchronous operation. PIC12F683 6.1 Timer1 Modes of Operation Timer1 can operate in one of three modes: 16-bit timer with prescaler 16-bit synchronous counter 16-bit asynchronous counter In Timer mode, Timer1 is incremented on every instruction cycle. In Counter mode, Timer1 is incremented on the rising edge of the external clock input T1CKI. In addition, the Counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. Timer1 gate source.
Legend Readable bit - n Value at POR 2004 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 (1) (2) /4) OSC W Writable bit U Unimplemented bit, read as 0 1 Bit is set 0 Bit is cleared Preliminary PIC12F683 R/W-0 R/W-0 R/W-0 T1SYNC TMR1CS TMR1ON bit Bit is unknown DS41211B-page 43. PIC12F683 6.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can gen- erate an interrupt on overflow, which will wake-up the processor.
Watchdog Timer Reset or Brown-out Reset) TMR2 is not cleared when T2CON is written. R/W-0 R/W-0 R/W-0 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 W Writable bit U Unimplemented bit, read as 0 1 Bit is set 0 Bit is cleared Preliminary PIC12F683 /4) has a prescale option OSC R/W-0 R/W-0 R/W-0 bit Bit is unknown DS41211B-page 45.
PIC12F683 7.2 Timer2 Interrupt The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register.
The PR2 register is initialized to FFh upon Reset. FIGURE 7-1: TIMER2 BLOCK DIAGRAM. A block diagram of the various comparator configurations is shown in Figure 8-3. R-0 U-0 R/W-0 R/W-0 CINV CIS W Writable bit U Unimplemented bit, read as 0 1 Bit is set 0 Bit is cleared Preliminary PIC12F683 R/W-0 R/W-0 R/W-0 CM2 CM1 CM0 bit Bit is unknown DS41211B-page 47. PIC12F683 8.1 Comparator Operation A single comparator is shown in Figure 8-1 along with the relationship between the analog input levels and the digital output.
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When the analog input at V than the analog input V -, the output of the comparator digital low level. When the analog input at V. GP1/CIN- A COUT GP0/CIN A GP2/COUT D Multiplexed Input with Internal Reference CM 110 GP1/CIN- A COUT GP0/CIN A GP2/COUT D CIS Comparator Input Switch (CMCON0) Preliminary PIC12F683 Off (Read as 0) COUT From CV Module REF CIS 0 CIS 1 COUT From CV Module REF CIS 0 CIS 1 COUT From CV Module REF.
PIC12F683 FIGURE 8-4: COMPARATOR OUTPUT BLOCK DIAGRAM CMSYNC To TMR1 To COUT pin To Data Bus RD CMCON Set CMIF bit Note 1: Comparator output is latched on falling edge of T1 clock source. REGISTER 8-2: CMCON1 COMPARATOR CONTROL REGISTER 1 (ADDRESS: 1Ah) U-0 bit 7 bit 7-2: Unimplemented: Read as 0 bit 1. Timer1 increments on the rising edge of its clock source. See Figure 8-4, Comparator Output Block Diagram and Figure 6-1, Timer1 on the PIC12F683 Block Diagram for more information recommended to synchronize the comparator with Timer1 by setting the CMSYNC bit when the compara- tor is used as the Timer1 gate source. This ensures Timer1 does not miss an increment if the comparator changes during an increment. PIC12F683 8.6 Comparator Reference The comparator module also allows the selection of an internally generated voltage reference for one of the comparator inputs. The VRCON register, Register 8-3, controls the voltage reference module shown in Figure 8-5.
8.6.1 CONFIGURING THE VOLTAGE REFERENCE The voltage reference can output 32 distinct voltage levels high range and low range. Enable bit drain and CV DD Value Selection 0 VR (VR/24 REF (VR/32 REF Writable bit U Unimplemented bit, read as 0 1 Bit is set 0 Bit is cleared Preliminary PIC12F683 R/W-0 R/W-0 R/W-0 VR2 VR1 VR0 bit REF Bit is unknown DS41211B-page 53. PIC12F683 TABLE 8-2: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Address Name Bit 7 Bit 6 0Bh/8Bh INTCON GIE PEIE 0Ch PIR1 EEIF ADIF CCP1IF 19h CMCON0 COUT 1Ah CMCON1 85h TRISIO TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 8Ch PIE1 EEIE.
The converter generates a binary result via successive approximation and stores the result in a 10-bit register. The voltage reference (A/D) allows used in the conversion is software selectable to either voltage applied by the V DD shows the block diagram of the A/D on the PIC12F683 VCFG 0 V VCFG 1 REF A/D GO/DONE.
PIC12F683 TABLE 9-1: T vs. DEVICE OPERATING FREQUENCIES AD A/D Clock Source ( Operation ADCS OSC 000 4 T 100 OSC 8 T 001 OSC 16 T 101 OSC 32 T 010 OSC 64 T 110 OSC A/D RC x11 Legend: Shaded cells are outside of recommended range. Note 1: The A/D RC source has a typical T. ADRESH and ADRESL registers are Loaded, GO bit is Cleared, ADIF bit is Set, Holding Capacitor is Connected to Analog Input ADRESH bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 Preliminary PIC12F683 sample. Instead, the ADRESL LSB bit 0 Unimplemented: Read as ‘.
PIC12F683 REGISTER 9-1: ADCON0 A/D CONTROL REGISTER (ADDRESS: 1Fh) R/W-0 R/W-0 ADFM VCFG bit 7 bit 7 ADFM: A/D Result Formed Select bit 1 Right justified 0 Left justified bit 6 VCFG: Voltage Reference bit pin REF bit 5-4 Unimplemented: Read as 0 bit 3-2 CHS: Analog Channel Select bits. Legend Readable bit - n Value at POR 2004 Microchip Technology Inc. R/W-0 R/W-0 R/W-1 ADCS1 ADCS0 ANS3 ( Writable bit U Unimplemented bit, read as 0 1 Bit is set 0 Bit is cleared Preliminary PIC12F683 R/W-1 R/W-1 R/W-1 ANS2 ANS1 ANS0 bit Bit is unknown DS41211B-page 59. PIC12F683 9.1.7 CONFIGURING THE A/D After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRISIO bits selected as inputs. To determine sample time, see Section 15.0 Electri- cal Specifications. After this sample time has elapsed, the A/D conversion can be started.
HOLD V DD Sampling Switch LEAKAGE V 0.6V T ± 500 Preliminary PIC12F683, see ACQ ® Mid-Range MCU Family Reference SS C HOLD DAC capacitance 120 Sampling Switch (k ) DS41211B-page 61. This allows the SLEEP instruction to be executed, thus eliminating much of the switching noise from the conversion. When the conversion is complete, the GO/DONE bit is cleared and the result is loaded into the ADRESH:ADRESL registers. FIGURE 9-5: PIC12F683 A/D TRANSFER FUNCTION 3FFh 3FEh 3FDh 3FCh 3FBh.
CHS1 CHS0 GO/DONE TRISIO1 CMIE OSFIE TMR2IE ADCS0 ANS3 ANS2 ANS1 Preliminary PIC12F683 Value on Value on: Bit 0 all other POR, BOD Resets GP0 -xx xxxx -uu uuuu GPIF 0000 0000 0000 0000 TMR1IF 000- 0000 000- 0000 xxxx xxxx uuuu uuuu ADON. PIC12F683 NOTES: DS41211B-page 64 Preliminary 2004 Microchip Technology Inc. EEDAT EEADR EEDAT holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. PIC12F683 has 256 bytes of data EEPROM with an address range from 0h to FFh. REGISTER 10-1: EEDAT EEPROM DATA REGISTER (ADDRESS: 9Ah). PIC12F683 10.1 EECON1 and EECON2 Registers EECON1 is the control register with four low-order bits physically implemented.
The upper four bits are non- implemented and read as 0. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software. They are cleared in hardware at completion of the read or write operation. If proper refreshes occurred, then the lone memory location would have to be refreshed six times for the data to remain correct.
Preliminary PIC12F683;Bank 1;EEDAT not changed;from previous write;YES, Read the. PIC12F683 10.5 Protection Against Spurious Write There are conditions when the user may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-up Timer (64 ms duration) EEPROM write. U-0 R/W-0 R/W-0 R/W-0 DC1B1 DC1B0 CCP1M3 W Writable bit U Unimplemented bit, read as 0 1 Bit is set 0 Bit is cleared Preliminary PIC12F683 CCP MODE TIMER RESOURCES REQUIRED Timer Resource Timer1 Timer1 Timer2 R/W-0 R/W-0 R/W-0 CCP1M2 CCP1M1 CCP1M0 bit Bit is unknown DS41211B-page 69.
PIC12F683 11.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin GP2/AN2/T0CKI/INT/COUT/CCP1. An event is defined as one of the following and is configured by CCP1CON: Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge When a capture is made, the interrupt request flag bit, CCP1IF (PIR1 bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level.
For sensitive applications, disable the PWM module prior to modifying the duty cycle. 1.22 kHz 4.88 kHz 19.53 kHz 0xFFh 0xFFh 0xFFh Preliminary PIC12F683 F OSC log F TMR2 Prescale Value PWM bits log(2) 78.12 kHz 156.3 kHz 208.3 kHz 1. PIC12F683 TABLE 11-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Addr Name Bit 7 Bit 6 Bit 5 0Bh/ INTCON GIE PEIE T0IE 8Bh 0Ch PIR1 EEIF ADIF CCP1IF 11h TMR2 Timer2 Module Register 12h T2CON TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000. SPECIAL FEATURES OF THE CPU The PIC12F683 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection. These features are: Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Detect (BOD). PIC12F683 12.1 Configuration Bits The configuration bits can be programmed (read as 0), or left unprogrammed (read as 1) to select various device configurations as shown in Register 12-1.
These bits are mapped in program memory location 2007h. REGISTER 12-1: CONFIG CONFIGURATION WORD (ADDRESS: 2007h) FCMEN IESO. Memory (DS41204) for more information. FCAL2 FCAL1 FCAL0 POR1 W Writable bit U Unimplemented bit, read as 0 1 Bit is set 0 Bit is cleared Preliminary PIC12F683 memory space (2000h- Programming Specification POR0 BOD2 BOD1 BOD0 bit Bit is unknown. PIC12F683 12.3 Reset The PIC12F683 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) WDT Reset during normal operation c) WDT Reset during Sleep d) MCLR Reset during normal operation e) MCLR Reset during Sleep f) Brown-out Detect (BOD) Some registers are not affected in any Reset condition. For additional information, refer to the Application Note AN607, Power-up Trouble Shooting (DS00607).
12.3.2 MCLR PIC12F683 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses.
It should be noted that a WDT Reset does not drive MCLR pin low. Power-up Timer will be re-initialized. Once V rises above V BOD 64 ms Reset.
12.3.4.1 BOD Calibration The PIC12F683 stores the BOD calibration values in fuses located in the Calibration Word register (2008h). The Calibration Word register is not erased when using the specified bulk erase sequence in the PIC12F6XX/ register 16F6XX Memory (DS41204) and thus, does not require reprogramming. Then, bringing MCLR high will begin execution immediately (see Figure 12-5). This is useful for testing purposes or to synchronize more than one PIC12F683 device operating in parallel. Table 12-5 shows the Reset conditions for some special registers, while Table 12-4 shows the Reset conditions for all the registers. PIC12F683 FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR.
Preliminary PIC12F683 Wake-up from Sleep through Interrupt WDT Time-out uuuu uuuu uuuu uuuu uuuu uuuu ( (4) uuuq quuu uuuu uuuu -uu uuuu -u uuuu. PIC12F683 TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Register Address Power-on Reset EECON1 9Ch - x000 EECON2 9Dh - - ADRESL 9Eh xxxx xxxx ANSEL 9Fh 1111 1111 Legend unchanged unknown, unimplemented bit, reads as 0’ value depends on condition. Note goes too low, Power-on Reset will be activated and registers will be affected differently. Interrupts The PIC12F683 has 11 sources of interrupt: External Interrupt GP2/INT TMR0 Overflow Interrupt GPIO Change Interrupts 2 Comparator Interrupts A/D Interrupt Timer1 Overflow Interrupt Timer2 Match Interrupt EEPROM Data Write Interrupt Fail-Safe Clock Monitor Interrupt. PIC12F683 12.4.2 TMR0 INTERRUPT An overflow (FFh 00h) in the TMR0 register will set the T0IF (INTCON) bit. The interrupt can be enabled/disabled by setting/clearing (INTCON) bit. See Section 5.0 Timer0 Module for operation of the Timer0 module.
FIGURE 12-7: INTERRUPT LOGIC IOC-GP0 IOC0 IOC-GP1 IOC1 IOC-GP2 IOC2.